The present invention relates to flash memories and, more particularly, to the use, as reference cells, of flash memory cells not initially intended to be used for that purpose.
Flash memories are structured as rectangular arrays of memory cells. The cells are arranged in orthogonal bit lines and word lines. One or more bits of data are written to each cell by injecting sufficient electrical charge into a floating gate of the cell to place the cell's threshold voltage within a range of threshold voltages that represents the value of that bit or of those bits. A flash memory cell is read by comparing its threshold voltage to reference voltages that mark the boundaries between threshold voltage ranges. In the case of a NOR flash memory, the cells may be written and read individually. In the case of a NAND flash memory, the cells are written and read one page at a time, with each word line including a small integral number (typically one or two, generally no more than four) of pages. The word lines are grouped further into blocks, such that cells are erased an entire block at a time.
For historical reasons, writing data to a flash memory cell also is called “programming” the cell.
One of the most disturbing issues in operation of Flash memories is the changing of cells' threshold voltage with the time, due to leakage of charge from the cells' floating gates. This phenomenon also is known as “data retention shift”. Excess data retention shift may result in errors when reading data from a flash memory, if reading reference voltage levels have not been adjusted in accordance with this shift. However, how can one know how much the cell threshold voltage have been shifted due to data retention shift, or, in other words, how much should the reading reference voltages be adjusted?
One conventional approach for addressing this issue is to assign a certain number of cells in each page as reference cells, to program these cells with a-priori known data, and to “sense” these cells' voltage thresholds in order to evaluate the amount of shift that caused by data retention. Implementing such reference cells in a flash memory system greatly improves the system's ability to cope with the data retention shift phenomenon.
However, in order to be able to get a reliable estimate of the data retention shift using such reference cells, the number of such cells for each flash page is not small. At least several tens of reference cells are required for each voltage level. This is a significant number of cells, especially in “multi-level-cell” flash memory devices that store more than one bit per cell. Adding such a significant number of cells to a flash memory page obviously increases the flash die size and, therefore, the cost of the flash silicon substrate.
Hence, it would be highly advantageous to be able to implement reference cells without increasing the flash memory die size.